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Memory-Centric Computing in AI Era
Time / Place:
⏱️ 09/16 (Sat.) 11:00-11:30 at R0 - International Conference Hall
Abstract:
Deep learning techniques have demonstrated great success in many application domains such as computer vision, speech recognition, and natural language processing. It has been shown that the memory subsystem is the main bottleneck in executing DNN applications, including the capacity and bandwidth walls. This talk covers recent researches for tackling the memory wall challenges.
Biography:
- 楊佳玲 Chia-Lin Yang
Website: https://www.csie.ntu.edu.tw/~yangc/
- National Taiwan University (NTU) / Dept. of Computer Science and Information Engineering, Professor
- Chia-Lin Yang received the Ph.D. degree from Duke University in 2001. Dr. Yang joined the Department of Computer Science and Information Engineering at NTU (National Taiwan University) in 2001. She joined the Department of Computer Science and Information Engineering at National Taiwan University at 2001. She is currently the Deputy Executive Director of Office of Science and Technology Policy at NSTC (National Science and Technology Policy). She was the Director of the Delta-NTU Joint Research Center at NTU from 2020 to 2023 and the Director of Graduate Institute of Networking and Multimedia at NTU from 2016 to 2019. Dr. Yang’s research focus is in the area of the system-level design methodology and computer architecture, with emphasis on the low-power system and memory hierarchy/SSD storage. Dr. Yang is currently serving as the Editor-in-Chief for IEEE Computer Architecture Letters, and the Program Co-chair for DAC 2024.